Since non-volatile memory devices are possible to electrically erase and store data, and the storage of data is possible without power supply, their applications have been increased in various fields. Such non-volatile memory devices are representatively classified into a NAND-type and a NOR-type. NAND-type memory cells are mainly used for storing data, and NOR-type memory cells are mainly used for booting.
A NOR-type non-volatile memory device is provided with a structure in which a plurality of memory cells each having a single transistor are connected in parallel to a bit line, and only a memory cell transistor is connected between a drain connected to the bit line and a source connected to a common source line. The NOR-type non-volatile memory device has an advantage in that the current of the memory cell is high and a high-speed operation is possible, while the NOR-type non-volatile memory device has a disadvantage in that an area occupied by the contact of the bit line and source line is broad so that high integration is difficult.
If the threshold voltage of the memory cell transistor becomes lower than a voltage (usually 0V) applied to a word line of a non-selection memory cell since the memory cells are connected in parallel to the bit line in the NOR-type non-volatile memory device, a current flows between the source and the drain regardless of the on/off of the selection memory cell so that there occurs malfunction in that all the memory cells are read in an on state. In order to solve such a problem, there has been suggested a non-volatile memory device provided with a structure generally called as a split gate type.
Meanwhile, non-volatile memory devices may be classified into a flash memory device with a lamination structure of a FLOTOX structure and a SONOS device provided with a multi-layered gate insulation film on a structure similar to a MOS transistor. Since the gate insulation film of the SONOS device is a multi-layered insulation film for electric charge storage, in which a charge is stored in a deep level trap, the SONOS device is superior to the flash memory device in view of reliability, and writing and erasing operations are possible under a low voltage.
FIGS. 1 to 3 are views illustrating a method of manufacturing a conventional split gate type non-volatile memory device.
Referring to FIG. 1, a device isolation film (not shown) is formed on a semiconductor substrate 10 to define an active region 11, and an electric charge storage layer, a first conductive film and a capping film are formed in the active region 11. In the electric charge storage layer, an insulation film with a high trap density is interposed between tunnel and blocking insulation films, and a lamination structure of a silicon oxide-silicon nitride-silicon oxide film (ONO film) is generally used. Moreover, a structure with a silicon oxide film serving as a buffer layer and a silicon nitride film servicing as a hard mask layer laminated therein is used as the capping film.
The capping film and the first conductive film and the electric charge storage layer are sequentially patterned to form a first conductive film pattern 16 having an electric charge storage layer 14 with an ONO structure interposed between the active region 11 and the first conductive film pattern 16, and a capping film pattern with oxide film and nitride film patterns 18 and 20 laminated on the first conductive pattern 16.
Referring to FIG. 2, a sidewall insulation film 22 is formed on a sidewall of the first conductive pattern 16, and a gate insulation film 24 is formed on the active region 11. Thereafter, a second conductive film 26 is conformally formed on the gate insulation film 24. At this time, a groove G is formed between the first conductive patterns 16 on the second conductive film 26 to form a sidewall of the second conductive film 26 (see FIG. 4a). Further, a photoresist pattern 28 is formed on the second conductive film 26.
Referring to FIG. 3, the second conductive film 26 is patterned using the photoresist pattern 28 as an etching mask such that the active region 11 between the neighboring first conductive film patterns 16 is exposed. The second conductive film 26 is generally removed through anisotrophic etching, in which there is a case where the etching is not smoothly performed because a polymer or residual product piles up while the anisotrophic etching is progressing on the sidewall of the second conductive film 26 within the groove G. As a result, when even the gate insulation film 24 is exposed by etching the second conductive film 26, conductive stringers 30 remain on the substrate. In a case where time for overetching is prolonged in order to completely remove the conductive stringers 30 formed on the substrate, the substrate may be damaged. On the contrary, unless the conductive stringers 30 are not completely removed, a defect 30a preventing the formation of a silicide and a contact pattern is produced as shown in FIG. 4c so that resistance in an active region is increased and contact resistance is also increased. Further, the defect 30a may result in the production of particles in a subsequent process.